1. Field of the Invention
The present invention relates to semiconductor memory devices, and more specifically to memory devices that have a low or zero consumption "standby" mode.
2. Description of Related Art
In a conventional memory device that uses a floating gate NMOS transistor with source and drain terminals as the elementary cell, the modulation of the threshold voltage of the cell is used to distinguish two logic states. A first logic state (e.g., logic "1"), is characteristic of a virgin cell and corresponds to the case in which the floating gate does not contain a charge, and another logic state (e.g., logic "0") corresponds to the case in which the floating gate stores sufficient electrons to determine a macroscopic increase in the threshold voltage and identify a programmed state of the memory cell.
In the reading phase, the memory cell is usually polarized with a gate source voltage equal to the supply voltage of the device (i.e., the source terminal is grounded and the drain terminal is at about 1 V). If the cell is written, the threshold voltage is above Vcc and therefore current does not flow. On the other hand, if the cell is erased, the threshold voltage must be such that current flows. The distribution of the cells after electrical erasure is typically between about 0.5 V and 2.5 V. The lower of the values is determined by the necessity to guarantee the absence of depleted cells and to avoid damage to the thin oxide of the floating gate transistor in the writing phase, and the higher of the values is determined by the intrinsic width of the distribution.
With low supply voltages (e.g., with Vcc values of around 2.5 V), the erased cells with thresholds near the upper boundary of the distribution do not drain sufficient current and therefore cannot be read correctly as storing logic "1". This problem can be overcome by providing a boost voltage to the row of cells. More specifically, a higher voltage is supplied to the Vcc supply and to the gate of the cell to be read, while the distribution of the thresholds remains the same. There are various conventional devices that use methods of voltage boosting.
1) Continuous Boost
When a read is to be carried out in a device using continuous boost, suitable clock impulses are supplied to the boost circuit to force the charge of a boost capacity and take the row to a voltage higher than Vcc. This method has an advantage in that the boost capacity need not be very large because the boosted voltage is produced by a series of small increases. However, for this same reason the amount of time necessary to initially charge the boost capacity is very high. Therefore, there is an increase in both the memory access time after the switch-off phase (i.e., power down) and the memory access time after a standby phase. In both of these phases, all the circuits of the memory device are switched off in order to limit consumption. To obviate the delay after a standby phase, it is possible to utilize a second smaller boost that keeps the main capacitor charged during standby. However, this increases the demand for current in this phase.
2) Impulse Boost
Devices using impulse boost solution a very large boost capacity is provided because this is necessary to increase the supply voltage of the whole supply of the row decoder. Furthermore, this capacity must be charged in a single strike and at the correct moment (i.e., when reading of a well-defined memory location is requested). On the other hand, the impulse boost method resolves increased access time out of standby and current consumption problems.
In semiconductor memories such as those of the EPROM and FLASH type, in order to be able to use devices having a few defective bits, redundancy circuitry is provided. This allows for a re-addressing of the memory in order to substitute working addresses in an added matrix portion for the addresses containing the defective bits. In order to contain the information for the substituted addresses in the memory matrix, memory cells (e.g., EPROM or FLASH) that are programmed during EWS (Electrical Wafer Sort) are used. Such cells are known as UPROM cells and during operation are read before carrying out any programming of the memory to allow for correct identification of the substituted addresses.
Nearly all digital electronic devices have a problem correctly resetting at the moment the power is switched on. There are conventional circuits, which are known as Power-On-Reset (POR) circuits, that are dedicated to the generation of a reset signal POR at the moment an electronic device switches on. During operation, at the moment that the voltage supply ramp Vdd terminates, the device must be ready to operate without any further commands (based on industry specifications for nonvolatile memory devices). This means that the memory must be ready to be interrogated for the contents of a selected memory location.
Thus, it is necessary to have already read the UPROM contents (i.e., a part of the Vdd ramp must be utilized to read the UPROM bank). For this reason, the trigger value of the reset signal POR that starts the reading of the UPROMs must chosen to be lower than Vdd. Furthermore, in positioning the trigger threshold of the reset signal POR, the noise margin must be considered with respect to variations in the supply voltage. For example, if the trigger threshold is set too high, the high threshold could cause the device to reset itself during typical Vdd noise.
With these considerations in mind, let us consider a non-volatile memory that requires a voltage boost and has zero consumption in the standby phase. With these requirements, the boost method that is used must be of the impulse one stroke type.
With this type of boost, the boost capacitor must be recharged after each reading.
Furthermore, for an asynchronous-type memory, the boost phases must be accurately timed and require a start signal ATD. If the memory device is designed to be read between 2.7 V and 3.8 V, the device is designed to work over the range covered by conventional specifications (e.g., the memory could be read from 2.3 V to 4 V). With such conditions, the value of the reset signal POR is typically set at around 1.8 V.
In accordance with the current requirements for the device, the user can supply the desired addresses when the device is not receiving current, with the supply only later switching on. Therefore, the reset signal POR must start the reading once the Vdd voltage has reached a sufficient value. If reading is started with a Vdd voltage that is too low, the reading operation would not be successful. Further, the user does not modify the addresses so there would not be another reading of the data. In other words, once the working value of the supply is reached, there is no signal to restart the reading operation so the user reads incorrect data.